integrated circuit systems, inc. general description features ics9179b-01 block diagram pentiumpro is a trademark of intel corporation i 2 c is a trademark of philips corporation low skew buffers 9179b-01 rev c 05/18/98 pin configuration the ics9179b-01 generates sdram clock buffers required for high speed risc or cisc microprocessor systems such as intel pentiumpro or pentium ii. an output enable is provided for testability. the device is a buffer with low output to output skew. this is a fanout buffer device, not using an internal pll. this buffer can also be a feedback to an external pll stage for phase synchronization to a master clock. the individual clock outputs are addressable through i 2 c to be enabled, or stopped in a low state for reduced emi when the lines are not needed. ? high speed, low noise non-inverting (0:17) buffer for sdram clock buffer applications. ? supports up to four sdram dimms ? synchronous clocks skew matched to 250 ps window on sdram. ? i 2 c serial configuration interface to allow individual clocks to be stopped. ? multiple vdd, vss pins for noise reduction ? tri-state pin for testing ? custom configurations available ? 3.0v ? 3.7v supply range ? 48-pin ssop package 48-pin ssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9179b-01 pin descriptions power groups vdd = power supply for sdram buffer vdds = power supply for i 2 c circuitry pin number pin name type description 4, 5, 8, 9 sdram (0:3) out sdram byte 0 clock outputs 1 13, 14, 17, 18 sdram (4:7) out sdram byte 1 clock outputs 1 31, 32, 35, 36 sdram (8:11) out sdram byte 2 clock outputs 1 40, 41, 44, 45 sdram (12:15) out sdram byte 3 clock outputs 1 21, 28 sdram (16:17) out sdram clock outputs useable for feedback. 1 11 buf_in in input for buffers 38 oe in tri-states all outputs when held low. has internal pull-up. 2 24 sdata i/o data pin for i 2 c circuitry 3 25 sclk i/o clock pin for i 2 c circuitry 3 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 vdd pwr 3.3v power supply for sdram buffer 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 gnd pwr ground for sdram buffer 23 vdds pwr 3.3v power supply for i 2 c circuitry 26 gnds pwr ground for i 2 c circuitry 1, 2, 47, 48 n/c - pins are not internally connected notes: 1. at power up all eighteen sdram outputs are enabled and active. 2. oe has a 100k ohm internal pull-up resistor to keep all outputs active. 3. the sdata and sclk inputs both also have internal pull-up resistors with values above 100k ohms as well for complete platform flexibility. ground groups gnd = ground for sdram buffer gnds = ground for i 2 c circuitry
3 ics9179b-01 vdd this is the power supply to the internal core logic of the device as well as the clock output buffers for sdram(0:17). this pin operates at 3.3v volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. gnd this is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. sdram(0:17) these output clocks are use to drive dynamic ram?s and are low skew copies of the cpu clocks. the voltage swing of the sdram?s output is controlled by the supply voltage that is applied to vdd of the device, operates at 3.3 volts. i 2 c the sdata and sclock inputs are use to program the device. the clock generator is a slave-receiver device in the i 2 c protocol. it will allow read-back of the registers. see configuration map for register functions. the i 2 c specification in philips i 2 c peripherals data handbook (1996) should be followed. buf_in input for fanout buffers (sdram 0:17). oe oe tristates all outputs when held low. vdds this is the power supply to i 2 c circuitry. gnds this is the ground to i 2 c circuitry. technical pin function descriptions
4 ics9179b-01 serial configuration command bitmaps byte 0: sdram clock register a. for the clock generator to be addressed by an i 2 c controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte. b. the clock generator is a slave/receiver i 2 c component. it can "read back "(in philips i 2 c protocol) the data stored in the latches for verification. (set r/w# to 1 above). there is no byte count supported, so it does not meet the intel smb piix4 protocol. c. the data transfer rate supported by this clock generator is 100k bits/sec (standard mode) d. the input is operating at 3.3v logic levels. e. the data byte format is 8 bit bytes. f. to simplify the clock generator i 2 c interface, the protocol is set to use only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. g . in the power down mode (pwr_dwn# low), the sdata and sclk pins are tristated and the internal data latches maintain all prior programming information. h. at power-on, all registers are set to a default condition. bytes 0 through 2 default to a 1 (enabled output state). general i 2 c serial interface information notes: 1 = enabled; 0 = disabled, outputs held low then byte 0, 1, 2, etc in sequence until stop. clock generator address (7 bits) ack + 8 bits dummy command code ack + 8 bits dummy byte count ack a(6:0) & r/w# d2 (h) bit pin# pwd description bit7 18 1 sdram7 (act/inact) bit6 17 1 sdram6 (act/inact) bit5 14 1 sdram5 (act/inact) bit4 13 1 sdram4 (act/inact) bit3 91 sdram3 (act/inact) bit2 8 1 sdram2 (act/inact) bit1 5 1 sdram1 (act/inact) bit0 4 1 sdram0 (act/inact) byte 0, 1, 2, etc in sequence until stop. clock generator address (7 bits) ack byte 0 ack byte 1 ack a(6:0) & r/w# d3 (h) note: pwd = power-up default
5 ics9179b-01 byte 1: sdram clock register functionality notes: 1 = enabled; 0 = disabled, outputs held low byte 2: pciclk clock register notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pwd description bit 7 28 1 sdram17 (act/inact) bit 6 21 1 sdram16 (act/inact) bit 5 - 1 reserved bit 4 - 1 reserved bit 3 - 1 reserved bit 2 - 1 reserved bit 1 - 1 reserved bit 0 - 1 reserved oe# sdram (0:3) sdram (4:7) sdram (8:11) sdram (12:15) sdram (16:17) 0 hi-z hi-z hi-z hi-z hi-z 1 1 x buf_in 1 x buf_in 1 x buf_in 1 x buf_in 1 x buf_in bit pin# pwd description bit 7 45 1 sdram15 (act/inact) bit 6 44 1 sdram14 (act/inact) bit 5 41 1 sdram13 (act/inact) bit 4 40 1 sdram12 (act/inact) bit 3 36 1 sdram11 (act/inact)) bit 2 35 1 sdram10 (act/inact) bit 1 32 1 sdram9 (act/inact) bit 0 31 1 sdram8 (act/inact)) ics9179b-01 power management the values below are estimates of target specifications. condition max 3.3v supply consumption max discrete cap loads vdd = 3.465v all static inputs = vdd or gnd no clock mode (buf_in - vdd1 or gnd) i 2 c circuitry active 3ma active 66mhz (buf_in = 66.66mhz) 115ma active 100mhz (buf_in = 100.00mhz) 180ma note: pwd = power-up default
6 ics9179b-01 absolute maximum ratings supply v oltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input & supply t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5ua i il v in = 0 v; inputs with no pull-up resistors -5 ua i il v in = 0 v; inputs with 100k pull-up resistors -60 -33 ua i dd1 c l = 0 pf; f in @ 66m 80 120 ma i dd2 c l = 0 pf; f in @ 100m 120 180 ma i dd3 c l = 30 pf; rs=33 w ; f in @ 66m 180 260 ma i dd4 c l = 30 pf; rs=33 w ; f in @ 100m 240 360 ma i dd5 stopped, input at 0 or vdd 500 a input frequency f i 1 v dd = 3.3 v; all outputs loaded 10 150 mhz input capacitance c in 1 logic inputs 5 pf 1 guaranteed by design, not 100% tested in production. input low current operating supply current
7 ics9179b-01 electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output impedance r dsp v o = v dd *(0.5) 10 24 w output impedance r dsn v o = v dd *(0.5) 10 24 w output high voltage v oh i oh = -36 ma 2.4 3 v output low voltage v ol i ol = 23 ma 0.27 0.4 v output high current i oh v oh = 2.0 v -115 -54 ma output low current i ol v ol = 0.8 v 40 57 ma ris e time 1 t r v ol = 0.4 v, v oh = 2.4 v 0.95 1.33 ns fall time 1 t f v oh = 2.4 v, v ol = 0.4 v 0.95 1.33 ns duty cycle 1 d t v t = 1.5 v 45 51 55 % skew 1 t sk v t = 1.5 v 110 250 ps t prop v t = 1.5 v 1 5 6 ns propagation 1 t propen v t = 1.5 v 1 8 ns t propdis v t = 1.5 v 18ns 1 guarenteed by design, not 100% tested in production.
8 ics9179b-01 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. capacitor values: all unmarked capacitors are 0.01f ceramic
9 ics9179b-01 ssop package ordering information ICS9179BF-01 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 a2 .088 .090 .092 b .008 .010 .0135 c.005- .010 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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